Main Page Modules Alphabetical List Data Structures File List Data Fields Globals # IXP425 OS Cache MMU (IxOsCacheMMU) API This service provides services to the access components and codelets to abstract out any cache coherency issues and mmu mappings. More...
## Defines
#define | IX_ACC_CACHE_ENABLED
| This macro enable cached memory in Access layers.
#define | IX_ACC_DRV_DMA_MALLOC(size)
| Allocate memory for driver use, that will be shared between XScale and NPE's.
#define | IX_ACC_DRV_DMA_FREE(ptr, size)
| Free memory allocated from IX_ACC_DRV_DMA_MALLOC.
#define | IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr)
| Return a virtual address for the provided physical address.
#define | IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr)
| Return a physical address for the provided virtual address.
#define | IX_XSCALE_CACHE_LINE_SIZE
| IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.
#define | IX_ACC_DRAM_PHYS_OFFSET
| PHYS_OFFSET = Physical DRAM offset..
#define | IX_ACC_DATA_CACHE_INVALIDATE(addr, size)
| Invalidate a cache range.
#define | IX_ACC_DATA_CACHE_FLUSH(addr, size)
| Flush a cache range to physical memory.
## Functions
void * | ixOsServCacheDmaAlloc (UINT32 size)
| Allocate memory for driver use, that will be shared between XScale and NPE's.
void | ixOsServCacheDmaFree (void *ptr, UINT32 size)
| Free memory allocated from ixOsServCacheDmaAlloc.
## Detailed Description This service provides services to the access components and codelets to abstract out any cache coherency issues and mmu mappings. ## Define Documentation
#define IX_ACC_CACHE_ENABLED
| This macro enable cached memory in Access layers. When defined, this macro enable the use of cached memory in the access layers. To disable cache on mbufs, #undef the macro Definition at line 89 of file IxOsCacheMMU.h.
#define IX_ACC_DATA_CACHE_FLUSH | ( | addr,
|  | size |  | ) |
| Flush a cache range to physical memory. Flush a cache range to physical memory. Note: This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to read from. Entire Cache lines will be flushed. If memory space used is non cached, then this function does may be null. Functionality required: Non-Cached space : Flush CPU WB, No cache Flush. Write Through Enabled : Flush CPU WB, No cache Flush. Copy Back Enabled : Flush CPU WB, Invalidate area specified Attention: There are different implementations for this macro Linux OS implementation: #define IX_ACC_DATA_CACHE_FLUSH(addr,size) clean_dcache_range((__u32)addr, (__u32)addr + size ) VxWorks OS implementation: #define IX_ACC_DATA_CACHE_FLUSH(addr,size) do { cacheFlush(DATA_CACHE, addr, size); cachePipeFlush(); } while(0) VxWorks OS implementation (write-through mode): #define IX_ACC_DATA_CACHE_FLUSH(addr,size) cachePipeFlush(); default implementation (uncached memory): #define IX_ACC_DATA_CACHE_FLUSH(addr,size) Definition at line 364 of file IxOsCacheMMU.h.
#define IX_ACC_DATA_CACHE_INVALIDATE | ( | addr,
|  | size |  | ) |
| Invalidate a cache range. Invalidate a cache range. Note: This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to populate with data. Attention: The size argument must be a multiple of cacheline size, i.e. a multiple if 32bytes for the XSCALE. The argument shall be rounded up to the next 32byte boundry. Extreem care must be taken when invalidating cache lines due. If memory space used is non cached, then this function may be null. Functionality required: Non-Cached space : No functionality required. Write Through Enabled : Invalidate area specified Copy Back Enabled : Invalidate area specified Attention: There are different implementations for this macro Linux OS implementation: #define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) invalidate_dcache_range((__u32)addr, (__u32)addr + size ) VxWorks OS implementation: #define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) cacheInvalidate(DATA_CACHE, addr, size) default implementation: #define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) Definition at line 363 of file IxOsCacheMMU.h.
#define IX_ACC_DRAM_PHYS_OFFSET
| PHYS_OFFSET = Physical DRAM offset.. Attention: There are different implementations for this macro Linux OS implementation: #define IX_ACC_DRAM_PHYS_OFFSET (PHYS_OFFSET) VxWorks OS implementation: #define IX_ACC_DRAM_PHYS_OFFSET (0x00000000UL) Definition at line 352 of file IxOsCacheMMU.h.
#define IX_ACC_DRV_DMA_FREE | ( | ptr,
|  | size |  | ) |
  | Free memory allocated from IX_ACC_DRV_DMA_MALLOC. This function frees the memory allocated from IX_ACC_DRV_DMA_MALLOC. Parameters:
  void | * ptr - pointer to the memory area to be freed.
  UINT32 | size - number of bytes of memory allocated.
Returns: void See also: IX_ACC_DRV_DMA_MALLOC Definition at line 174 of file IxOsCacheMMU.h.
#define IX_ACC_DRV_DMA_MALLOC | ( | size |  | ) |
  | Allocate memory for driver use, that will be shared between XScale and NPE's. This macro is used allocate memory for driver use, that will be shared between XScale and NPE's. Note: The buffer allocated with have the system defined atributes, and as such the Invalidate and flush macros functionality must be updated. The buffer allocated is aligned on a cache line boundary. Parameters:
  UINT32 | size - number of bytes of memory requested.
Returns: void * Pointer to memory that can be used between XScale and NPE's. See also: IX_ACC_DRV_DMA_FREE Definition at line 155 of file IxOsCacheMMU.h.
#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION | ( | addr |  | ) |
| Return a physical address for the provided virtual address. This macro return a physical address for the provided virtual address Attention: There are different implementations for this macro Linux OS implementation: #define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) ((addr) ? virt_to_phys((void*)(addr)) : 0) VxWorks OS implementation: #define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) (addr) default implementation: #define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) (addr) Definition at line 362 of file IxOsCacheMMU.h.
#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION | ( | addr |  | ) |
| Return a virtual address for the provided physical address. This macro return a virtual address for the provided physical address. Attention: There are different implementations for this macro Linux OS implementation: #define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) ((addr) ? virt_to_phys((void*)(addr)) : 0) VxWorks OS implementation: #define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) (addr) default implementation: #define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) (addr) Definition at line 361 of file IxOsCacheMMU.h.
#define IX_XSCALE_CACHE_LINE_SIZE
| IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate. Definition at line 366 of file IxOsCacheMMU.h.
## Function Documentation
void* ixOsServCacheDmaAlloc | ( | UINT32 | size | ) |
  | Allocate memory for driver use, that will be shared between XScale and NPE's. Allocate memory for driver use, that will be shared between XScale and NPE's. Note: The buffer allocated with have the system defined atributes, and as such the Invalidate and flush macros functionality must be updated. The buffer allocated is aligned on a cache line boundary. Parameters:
  UINT32 | size - number of bytes of memory requested.
Returns: void * Pointer to memory that can be used between XScale and NPE's. See also: ixOsServCacheDmaFree
void ixOsServCacheDmaFree | ( | void * | ptr,
|  | UINT32 | size
| ) |
  | Free memory allocated from ixOsServCacheDmaAlloc. This function frees the memory allocated from ixOsServCacheDmaAlloc. Parameters:
  void | *ptr - pointer to the memory area to be freed.
  UINT32 | size - number of bytes of memory allocated.
Returns: void See also: ixOsServCacheDmaMalloc
Automatically generated from sources. © Intel Corp. 2003