Main Page Modules Alphabetical List Data Structures File List Data Fields Globals # IXP425 NPE-A (IxNpeA) API The Public API for the IXP425 NPE-A. More...
## Data Structures
struct | IxNpeA_NpePacketDescriptor
| HSS Packetized NpePacket Descriptor Structure. More...
struct | IxNpeA_RxAtmVc
| Rx Descriptor definition. More...
struct | IxNpeA_TxAtmVc
| Tx Descriptor definition. More...
## Defines
#define | IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
| ATM Message ID command to write the data to the offset in the Utopia Configuration Table.
#define | IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
| ATM Message ID command triggers the NPE to copy the Utopia Configuration Table to the Utopia coprocessor.
#define | IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
| ATM Message ID command triggers the NPE to read-back the Utopia status registers and update the Utopia Status Table.
#define | IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
| ATM Message ID command to read the Utopia Status Table at the specified offset.
#define | IX_NPE_A_MSSG_ATM_TX_ENABLE
| ATM Message ID command triggers the NPE to re-enable processing of any entries on the TxVcQ for this port.
#define | IX_NPE_A_MSSG_ATM_TX_DISABLE
| ATM Message ID command triggers the NPE to disable processing on this port.
#define | IX_NPE_A_MSSG_ATM_RX_ENABLE
| ATM Message ID command triggers the NPE to process any received cells for this VC according to the VC Lookup Table.
#define | IX_NPE_A_MSSG_ATM_RX_DISABLE
| ATM Message ID command triggers the NPE to disable processing for this VC.
#define | IX_NPE_A_MSSG_ATM_STATUS_READ
| ATM Message ID command to read the ATM status. The data is returned via a response message.
#define | IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
| HSS Message ID command writes the ConfigWord value to the location in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
#define | IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
| HSS Message ID command triggers the NPE to copy the contents of the HSS Configuration Table to the appropriate configuration registers in the HSS coprocessor for the port specified by hPort.
#define | IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
| HSS Message ID command triggers the NPE to return an HssErrorReadResponse message for HSS port hPort.
#define | IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
| HSS Message ID command triggers the NPE to reset internal status and enable the HssChannelized operation on the HSS port specified by hPort.
#define | IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
| HSS Message ID command triggers the NPE to disable the HssChannelized operation on the HSS port specified by hPort.
#define | IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
| HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
| HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
| HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
| HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
| HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB, HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
| HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
| HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS port hPort. (n=hPort).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
| HSS Message ID command triggers the NPE to reset internal status and enable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort.
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
| HSS Message ID command triggers the NPE to disable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort.
#define | IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
| HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS port hPort.(n=hPort).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).
#define | IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_MODE value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).
#define | IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Status field.
#define | IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
| ATM Descriptor structure offset for Receive Descriptor VC ID field.
#define | IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current Mbuf Size field.
#define | IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
| ATM Descriptor structure offset for Receive Descriptor ATM Header.
#define | IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf length.
#define | IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET
#define | IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer.
#define | IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer.
#define | IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer.
#define | IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Total Length.
#define | IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
| ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue.
#define | IX_NPE_A_RXDESCRIPTOR_SIZE
| ATM Descriptor structure offset for Receive Descriptor Size.
#define | IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Port.
#define | IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor RSVD.
#define | IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length.
#define | IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor ATM Header.
#define | IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain.
#define | IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data.
#define | IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain.
#define | IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Total Length.
#define | IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue.
#define | IX_NPE_A_TXDESCRIPTOR_SIZE
| ATM Descriptor structure offset for Transmit Descriptor Size.
#define | IX_NPE_MPHYMULTIPORT
| Define this macro to enable MPHY mode.
#define | IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
| The NPE reserves the High Watermark for its operation. But it must be set by the Xscale.
#define | IX_NPE_A_QMQ_ATM_TX_DONE
| Queue ID for ATM Transmit Done queue.
#define | IX_NPE_A_QMQ_ATM_TX0
| Queue ID for ATM transmit Queue in a single phy configuration.
#define | IX_NPE_A_QMQ_ATM_TXID_MIN
| Queue Manager Queue ID for ATM transmit Queue with minimum number of queue.
#define | IX_NPE_A_QMQ_ATM_TXID_MAX
| Queue Manager Queue ID for ATM transmit Queue with maximum number of queue.
#define | IX_NPE_A_QMQ_ATM_RX_HI
| Queue Manager Queue ID for ATM Receive high Queue.
#define | IX_NPE_A_QMQ_ATM_RX_LO
| Queue Manager Queue ID for ATM Receive low Queue.
#define | IX_NPE_A_QMQ_ATM_TX1
| Queue ID for ATM transmit Queue Multiphy from 1 to 11.
#define | IX_NPE_A_QMQ_ATM_TX2
#define | IX_NPE_A_QMQ_ATM_TX3
#define | IX_NPE_A_QMQ_ATM_TX4
#define | IX_NPE_A_QMQ_ATM_TX5
#define | IX_NPE_A_QMQ_ATM_TX6
#define | IX_NPE_A_QMQ_ATM_TX7
#define | IX_NPE_A_QMQ_ATM_TX8
#define | IX_NPE_A_QMQ_ATM_TX9
#define | IX_NPE_A_QMQ_ATM_TX10
#define | IX_NPE_A_QMQ_ATM_TX11
#define | IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
| Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger.
#define | IX_NPE_A_QMQ_HSS0_PKT_RX
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive.
#define | IX_NPE_A_QMQ_HSS0_PKT_TX0
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0.
#define | IX_NPE_A_QMQ_HSS0_PKT_TX1
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1.
#define | IX_NPE_A_QMQ_HSS0_PKT_TX2
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2.
#define | IX_NPE_A_QMQ_HSS0_PKT_TX3
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3.
#define | IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0.
#define | IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1.
#define | IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2.
#define | IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3.
#define | IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue.
#define | IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
| Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger.
#define | IX_NPE_A_QMQ_HSS1_PKT_RX
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive.
#define | IX_NPE_A_QMQ_HSS1_PKT_TX0
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0.
#define | IX_NPE_A_QMQ_HSS1_PKT_TX1
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1.
#define | IX_NPE_A_QMQ_HSS1_PKT_TX2
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2.
#define | IX_NPE_A_QMQ_HSS1_PKT_TX3
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3.
#define | IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0.
#define | IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1.
#define | IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2.
#define | IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3.
#define | IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue.
#define | IX_NPE_A_QMQ_ATM_FREE_VC0
| Hardware QMgr Queue ID for ATM Free VC Queue.
#define | IX_NPE_A_QMQ_ATM_FREE_VC1
#define | IX_NPE_A_QMQ_ATM_FREE_VC2
#define | IX_NPE_A_QMQ_ATM_FREE_VC3
#define | IX_NPE_A_QMQ_ATM_FREE_VC4
#define | IX_NPE_A_QMQ_ATM_FREE_VC5
#define | IX_NPE_A_QMQ_ATM_FREE_VC6
#define | IX_NPE_A_QMQ_ATM_FREE_VC7
#define | IX_NPE_A_QMQ_ATM_FREE_VC8
#define | IX_NPE_A_QMQ_ATM_FREE_VC9
#define | IX_NPE_A_QMQ_ATM_FREE_VC10
#define | IX_NPE_A_QMQ_ATM_FREE_VC11
#define | IX_NPE_A_QMQ_ATM_FREE_VC12
#define | IX_NPE_A_QMQ_ATM_FREE_VC13
#define | IX_NPE_A_QMQ_ATM_FREE_VC14
#define | IX_NPE_A_QMQ_ATM_FREE_VC15
#define | IX_NPE_A_QMQ_ATM_FREE_VC16
#define | IX_NPE_A_QMQ_ATM_FREE_VC17
#define | IX_NPE_A_QMQ_ATM_FREE_VC18
#define | IX_NPE_A_QMQ_ATM_FREE_VC19
#define | IX_NPE_A_QMQ_ATM_FREE_VC20
#define | IX_NPE_A_QMQ_ATM_FREE_VC21
#define | IX_NPE_A_QMQ_ATM_FREE_VC22
#define | IX_NPE_A_QMQ_ATM_FREE_VC23
#define | IX_NPE_A_QMQ_ATM_FREE_VC24
#define | IX_NPE_A_QMQ_ATM_FREE_VC25
#define | IX_NPE_A_QMQ_ATM_FREE_VC26
#define | IX_NPE_A_QMQ_ATM_FREE_VC27
#define | IX_NPE_A_QMQ_ATM_FREE_VC28
#define | IX_NPE_A_QMQ_ATM_FREE_VC29
#define | IX_NPE_A_QMQ_ATM_FREE_VC30
#define | IX_NPE_A_QMQ_ATM_FREE_VC31
#define | IX_NPE_A_QMQ_ATM_RXFREE_MIN
| The minimum queue ID for FreeVC queue.
#define | IX_NPE_A_QMQ_ATM_RXFREE_MAX
| The maximum queue ID for FreeVC queue.
#define | IX_NPE_A_QMQ_OAM_FREE_VC
| OAM Rx Free queue ID.
#define | IX_NPE_A_CHAIN_DESC_COUNT_MAX
| Maximum number of chained MBufs that can be chained together.
#define | GFC_MASK
| Mask to acess GFC.
#define | IX_NPE_A_ATMCELLHEADER_GFC_GET(header)
| return GFC from ATM cell header
#define | IX_NPE_A_ATMCELLHEADER_GFC_SET(header, gfc)
| set GFC into ATM cell header
#define | VPI_MASK
| Mask to acess VPI.
#define | IX_NPE_A_ATMCELLHEADER_VPI_GET(header)
| return VPI from ATM cell header
#define | IX_NPE_A_ATMCELLHEADER_VPI_SET(header, vpi)
| set VPI into ATM cell header
#define | VCI_MASK
| Mask to acess VCI.
#define | IX_NPE_A_ATMCELLHEADER_VCI_GET(header)
| return VCI from ATM cell header
#define | IX_NPE_A_ATMCELLHEADER_VCI_SET(header, vci)
| set VCI into ATM cell header
#define | PTI_MASK
| Mask to acess PTI.
#define | IX_NPE_A_ATMCELLHEADER_PTI_GET(header)
| return PTI from ATM cell header
#define | IX_NPE_A_ATMCELLHEADER_PTI_SET(header, pti)
| set PTI into ATM cell header
#define | CLP_MASK
| Mask to acess CLP.
#define | IX_NPE_A_ATMCELLHEADER_CLP_GET(header)
| return CLP from ATM cell header
#define | IX_NPE_A_ATMCELLHEADER_CLP_SET(header, clp)
| set CLP into ATM cell header
#define | STATUS_MASK
| Mask to acess the rxBitField status.
#define | IX_NPE_A_RXBITFIELD_STATUS_GET(rxbitfield)
| return the rxBitField status
#define | IX_NPE_A_RXBITFIELD_STATUS_SET(rxbitfield, status)
| set the rxBitField status
#define | PORT_MASK
| Mask to acess the rxBitField port.
#define | IX_NPE_A_RXBITFIELD_PORT_GET(rxbitfield)
| return the rxBitField port
#define | IX_NPE_A_RXBITFIELD_PORT_SET(rxbitfield, port)
| set the rxBitField port
#define | VCID_MASK
| Mask to acess the rxBitField vcId.
#define | IX_NPE_A_RXBITFIELD_VCID_GET(rxbitfield)
| return the rxBitField vcId
#define | IX_NPE_A_RXBITFIELD_VCID_SET(rxbitfield, vcid)
| set the rxBitField vcId
#define | CURRMBUFSIZE_MASK
| Mask to acess the rxBitField mbuf size.
#define | IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET(rxbitfield)
| return the rxBitField mbuf size
#define | IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET(rxbitfield, currmbufsize)
| set the rxBitField mbuf size
## Enumerations
enum | IxNpeA_AalType { IX_NPE_A_AAL_TYPE_INVALID, IX_NPE_A_AAL_TYPE_0_48, IX_NPE_A_AAL_TYPE_0_52, IX_NPE_A_AAL_TYPE_5, IX_NPE_A_AAL_TYPE_OAM }
| NPE-A AAL Type. More...
enum | IxNpeA_PayloadFormat { IX_NPE_A_52_BYTE_PAYLOAD, IX_NPE_A_48_BYTE_PAYLOAD }
| NPE-A Payload format 52-bytes & 48-bytes. More...
## Detailed Description The Public API for the IXP425 NPE-A. ## Define Documentation
#define CLP_MASK
| Mask to acess CLP. Definition at line 920 of file IxNpeA.h.
#define CURRMBUFSIZE_MASK
| Mask to acess the rxBitField mbuf size. Definition at line 999 of file IxNpeA.h.
#define GFC_MASK
| Mask to acess GFC. Definition at line 864 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_CLP_GET | ( | header |  | ) |
| return CLP from ATM cell header Definition at line 923 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_CLP_SET | ( | header,
|  | clp |  | ) |
| set CLP into ATM cell header Definition at line 927 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_GFC_GET | ( | header |  | ) |
| return GFC from ATM cell header Definition at line 867 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_GFC_SET | ( | header,
|  | gfc |  | ) |
| set GFC into ATM cell header Definition at line 871 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_PTI_GET | ( | header |  | ) |
| return PTI from ATM cell header Definition at line 909 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_PTI_SET | ( | header,
|  | pti |  | ) |
| set PTI into ATM cell header Definition at line 913 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_VCI_GET | ( | header |  | ) |
| return VCI from ATM cell header Definition at line 895 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_VCI_SET | ( | header,
|  | vci |  | ) |
| set VCI into ATM cell header Definition at line 899 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_VPI_GET | ( | header |  | ) |
| return VPI from ATM cell header Definition at line 881 of file IxNpeA.h.
#define IX_NPE_A_ATMCELLHEADER_VPI_SET | ( | header,
|  | vpi |  | ) |
| set VPI into ATM cell header Definition at line 885 of file IxNpeA.h.
#define IX_NPE_A_CHAIN_DESC_COUNT_MAX
| Maximum number of chained MBufs that can be chained together. Definition at line 837 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_RX_DISABLE
| ATM Message ID command triggers the NPE to disable processing for this VC. This command will be ignored for a VC already disabled Definition at line 138 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_RX_ENABLE
| ATM Message ID command triggers the NPE to process any received cells for this VC according to the VC Lookup Table. Re-issuing this command with different contents for a VC that is not disabled will cause unpredictable behavior. Definition at line 128 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_STATUS_READ
| ATM Message ID command to read the ATM status. The data is returned via a response message. Definition at line 146 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_TX_DISABLE
| ATM Message ID command triggers the NPE to disable processing on this port. This command will be ignored for a port already disabled Definition at line 117 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_TX_ENABLE
| ATM Message ID command triggers the NPE to re-enable processing of any entries on the TxVcQ for this port. This command will be ignored for a port already enabled Definition at line 107 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
| ATM Message ID command triggers the NPE to copy the Utopia Configuration Table to the Utopia coprocessor. Definition at line 81 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
| ATM Message ID command to write the data to the offset in the Utopia Configuration Table. Definition at line 73 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
| ATM Message ID command to read the Utopia Status Table at the specified offset. Definition at line 97 of file IxNpeA.h.
#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
| ATM Message ID command triggers the NPE to read-back the Utopia status registers and update the Utopia Status Table. Definition at line 89 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
| HSS Message ID command triggers the NPE to disable the HssChannelized operation on the HSS port specified by hPort. Definition at line 191 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
| HSS Message ID command triggers the NPE to reset internal status and enable the HssChannelized operation on the HSS port specified by hPort. Definition at line 183 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
| HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS port hPort. (n=hPort). Definition at line 199 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
| HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS port hPort. (n=hPort). Definition at line 207 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
| HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS port hPort. (n=hPort). Definition at line 215 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
| HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort). Definition at line 223 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
| HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB, HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values for HSS port hPort. (n=hPort). Definition at line 232 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
| HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS port hPort. (n=hPort). Definition at line 239 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
| HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS port hPort. (n=hPort). Definition at line 247 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
| HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS port hPort.(n=hPort). Definition at line 270 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe). Definition at line 278 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
| HSS Message ID command triggers the NPE to disable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort. Definition at line 263 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
| HSS Message ID command triggers the NPE to reset internal status and enable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort. Definition at line 256 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe). Definition at line 287 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe). Definition at line 295 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_MODE value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe). Definition at line 311 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
| HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe). Definition at line 303 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
| HSS Message ID command triggers the NPE to copy the contents of the HSS Configuration Table to the appropriate configuration registers in the HSS coprocessor for the port specified by hPort. Definition at line 167 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
| HSS Message ID command writes the ConfigWord value to the location in the HSS_CONFIG_TABLE specified by offset for HSS port hPort. Definition at line 158 of file IxNpeA.h.
#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
| HSS Message ID command triggers the NPE to return an HssErrorReadResponse message for HSS port hPort. Definition at line 175 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_FREE_VC0
| Hardware QMgr Queue ID for ATM Free VC Queue. There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to IX_NPE_A_QMQ_ATM_FREE_VC30 Definition at line 775 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_RX_HI
| Queue Manager Queue ID for ATM Receive high Queue. Definition at line 591 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_RX_LO
| Queue Manager Queue ID for ATM Receive low Queue. Definition at line 592 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_RXFREE_MAX
| The maximum queue ID for FreeVC queue. Definition at line 820 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_RXFREE_MIN
| The minimum queue ID for FreeVC queue. Definition at line 813 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_TX0
| Queue ID for ATM transmit Queue in a single phy configuration. Definition at line 546 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_TX1
| Queue ID for ATM transmit Queue Multiphy from 1 to 11. Definition at line 578 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_TX_DONE
| Queue ID for ATM Transmit Done queue. Definition at line 539 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_TXID_MAX
| Queue Manager Queue ID for ATM transmit Queue with maximum number of queue. Definition at line 590 of file IxNpeA.h.
#define IX_NPE_A_QMQ_ATM_TXID_MIN
| Queue Manager Queue ID for ATM transmit Queue with minimum number of queue. Definition at line 589 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
| Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger. Definition at line 609 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_RX
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive. Definition at line 616 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0. Definition at line 651 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1. Definition at line 658 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2. Definition at line 665 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
| Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3. Definition at line 672 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_TX0
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0. Definition at line 623 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_TX1
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1. Definition at line 630 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_TX2
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2. Definition at line 637 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_TX3
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3. Definition at line 644 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
| Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue. Definition at line 679 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
| Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger. Definition at line 691 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_RX
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive. Definition at line 698 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0. Definition at line 733 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1. Definition at line 740 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2. Definition at line 747 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
| Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3. Definition at line 754 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_TX0
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0. Definition at line 705 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_TX1
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1. Definition at line 712 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_TX2
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2. Definition at line 719 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_TX3
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3. Definition at line 726 of file IxNpeA.h.
#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
| Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue. Definition at line 761 of file IxNpeA.h.
#define IX_NPE_A_QMQ_OAM_FREE_VC
| OAM Rx Free queue ID. Definition at line 827 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET | ( | rxbitfield |  | ) |
| return the rxBitField mbuf size Definition at line 1002 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET | ( | rxbitfield,
|  | currmbufsize |  | ) |
| set the rxBitField mbuf size Definition at line 1006 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_PORT_GET | ( | rxbitfield |  | ) |
| return the rxBitField port Definition at line 974 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_PORT_SET | ( | rxbitfield,
|  | port |  | ) |
| set the rxBitField port Definition at line 978 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_STATUS_GET | ( | rxbitfield |  | ) |
| return the rxBitField status Definition at line 960 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_STATUS_SET | ( | rxbitfield,
|  | status |  | ) |
| set the rxBitField status Definition at line 964 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_VCID_GET | ( | rxbitfield |  | ) |
| return the rxBitField vcId Definition at line 988 of file IxNpeA.h.
#define IX_NPE_A_RXBITFIELD_VCID_SET | ( | rxbitfield,
|  | vcid |  | ) |
| set the rxBitField vcId Definition at line 992 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
| ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue. Current CRC value for a PDU Definition at line 419 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
| ATM Descriptor structure offset for Receive Descriptor ATM Header. Definition at line 354 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf length. RX - Initialized to zero. The NPE updates this field as each cell is received and zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize. Definition at line 365 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current Mbuf Size field. Number of bytes the current mbuf data buffer can hold Definition at line 347 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer. Pointer to the next byte to be read or next free location to be written. Definition at line 392 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer. The current mbuf pointer of a chain of mbufs. Definition at line 383 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer. Pointer to the next MBuf in a chain of MBufs. Definition at line 401 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_SIZE
| ATM Descriptor structure offset for Receive Descriptor Size. The size of the Receive descriptor Definition at line 428 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Status field. It is used for descriptor error reporting. Definition at line 328 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
| ATM Descriptor structure offset for Receive Descriptor Total Length. Total number of bytes written to the chain of MBufs by the NPE Definition at line 410 of file IxNpeA.h.
#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
| ATM Descriptor structure offset for Receive Descriptor VC ID field. It is used to hold an identifier number for this VC Definition at line 337 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue. Current CRC value for a PDU Definition at line 502 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor ATM Header. Definition at line 461 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length. TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer. The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a descriptor the TxDone queue, this field will equal zero. Definition at line 455 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data. Pointer to the next byte to be read or next free location to be written. Definition at line 477 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain. Definition at line 468 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain. Definition at line 484 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Port. Port identifier. Definition at line 437 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor RSVD. Definition at line 444 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_SIZE
| ATM Descriptor structure offset for Transmit Descriptor Size. Definition at line 509 of file IxNpeA.h.
#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
| ATM Descriptor structure offset for Transmit Descriptor Total Length. Total number of bytes written to the chain of MBufs by the NPE Definition at line 493 of file IxNpeA.h.
#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
| The NPE reserves the High Watermark for its operation. But it must be set by the Xscale. Definition at line 532 of file IxNpeA.h.
#define IX_NPE_MPHYMULTIPORT
| Define this macro to enable MPHY mode. Definition at line 516 of file IxNpeA.h.
#define PORT_MASK
| Mask to acess the rxBitField port. Definition at line 971 of file IxNpeA.h.
#define PTI_MASK
| Mask to acess PTI. Definition at line 906 of file IxNpeA.h.
#define STATUS_MASK
| Mask to acess the rxBitField status. Definition at line 957 of file IxNpeA.h.
#define VCI_MASK
| Mask to acess VCI. Definition at line 892 of file IxNpeA.h.
#define VCID_MASK
| Mask to acess the rxBitField vcId. Definition at line 985 of file IxNpeA.h.
#define VPI_MASK
| Mask to acess VPI. Definition at line 878 of file IxNpeA.h.
## Enumeration Type Documentation
enum IxNpeA_AalType
  | NPE-A AAL Type. Enumeration values:
  IX_NPE_A_AAL_TYPE_INVALID | Invalid AAL type.
  IX_NPE_A_AAL_TYPE_0_48 | AAL0 - 48 byte.
  IX_NPE_A_AAL_TYPE_0_52 | AAL0 - 52 byte.
  IX_NPE_A_AAL_TYPE_5 | AAL5.
  IX_NPE_A_AAL_TYPE_OAM | OAM.
Definition at line 1059 of file IxNpeA.h.
enum IxNpeA_PayloadFormat
  | NPE-A Payload format 52-bytes & 48-bytes. Enumeration values:
  IX_NPE_A_52_BYTE_PAYLOAD | 52 byte payload
  IX_NPE_A_48_BYTE_PAYLOAD | 48 byte payload
Definition at line 1071 of file IxNpeA.h.
Automatically generated from sources. © Intel Corp. 2003